EDN

FPGA design and verification solutions from Lattice and Aldec

The folks at Lattice Semiconductor and Aldec have announced a new OEM agreement that will deliver the only OEM FPGA mixed language simulator. Active-HDL Lattice Edition will be bundled with Lattice's ...
Business Wire

Aldec Cuts ASIC Design Prototype Bring-Up Time with HES-DVM’s Automatic Partitioning Tool and Faster HDL-to-FPGA Compilation Times

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced automatic FPGA partitioning to ...
EDN

Aldec FPGA simulation added to Altium Designer

Altium and Aldec have signed an OEM agreement that adds Aldec's FPGA simulation capabilities to Altium Designer. Electronics designers can now access Aldec's VHDL and Verilog simulation technology as ...
Design-Reuse

Aldec adds Documentation for Safety-Critical Designs in ALINT 2012.01

Henderson, NV – January 23, 2012 – Aldec, Inc., announces the release of ALINT 2012.01,a design rule checking application for HDL-based FPGA/ASIC designs. The new release adds documentation ...
Semiconductor Engineering

HW/SW Co-Verification For Hybrid Systems

Heterogeneous SoC architectures such as Zynq have become very popular recently due to the combination of programmable logic (FPGA) and processing system (ARM) integrated into a single chip. Developing ...
Electronic Design

Mixed-Language Simulator Serves FPGA Designers

In the Active-HDL Designer Edition, a low-cost mixed-language RTL simulator, designers gain a high-performance simulator for designs targeted at FPGAs. Basically, FPGA designers have been forced to ...
Semiconductor Engineering

FPGA VHDL Verification

This is actually possible – and with an average efficiency improvement of 20% to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented ...