Design-Reuse

AMBA 4 ACE for Heterogeneous Multiprocessing SoCs

AMBA 4 ACE adds system-level coherency support to the AMBA 4 specifications. By enabling cache coherency between the high- performance ARM Cortex-A15 MPCore processor and software-compatible high- ...
Electronic Design

Formal Techniques for Protocol Verification: A Case Study On Verifying the ARM ACE Protocol

More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol. Fig 1.
Semiconductor Engineering

Moving From AMBA ACE to CHI For Coherency

Introduced back in 2011, ACE (AXI Coherency Extensions) grew from the existing AXI protocol to satisfy the cache coherency maintenance demands of SoCs with multi core processors and shared caches in ...
Design-Reuse

Mentor Graphics Questa and Veloce Verification Platforms Add Cache Coherency and Interconnect Performance for ARM AMBA 5 CHI and AMBA 4 ACE Designs

WILSONVILLE, Ore., June 3, 2013 —Mentor Graphics Corp. (NASDAQ: MENT) today announced that cache coherent interconnect subsystem verification has been added to the Questa® and Veloce® platforms.