TOKYO — Toshiba Corp. has developed a one-transistor, no-capacitor cell structure that it claims solves the difficulties encountered in producing DRAMs in sub-0.1-micron process technology. The ...

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability issues, even ...

To push access times toward those of SRAM while achieving much higher densities, embedded DRAM needs a structure that differs from both commodity DRAM and conventional embedded DRAM. The challenge is ...

On June 4, 1968, Robert Dennard was granted a patent for a single transistor, single capacitor DRAM cell design idea. This doesn’t sound earth-shattering today, but back in the sixties, this was a ...

But if you eliminate the capacitor, where is the charge that represents the data bit stored? That's the magic of SOI. The active circuit layer is isolated from the substrate, so there's a capacitive ...