Electronic Design

CXL: Coherency, Memory, and I/O Semantics on PCIe Infrastructure

Gain insight into the CXL specification. Learn how CXL supports dynamic multiplexing between a rich set of protocols that includes I/O (CLX.io, based on PCIe), caching (CXL.cache), and memory (CXL.mem ...
TweakTown

Intel's new Sapphire Rapids CPU: PCIe 5.0 tech, 64GB of HBM2e memory

We are finding out some more information on Intel's next-gen Sapphire Rapids architecture, with the next-gen Xeon platform set to pack some juicy specs and technologies when it drops. The new tease is ...
TechSpot

Samsung introduces industry's first CXL module featuring DDR5 memory and PCIe 5.0 connectivity

In brief: Samsung has recently announced a DDR5 memory expander that uses CXL, a new open standard for CPU-to-device and CPU-to-memory interconnection that benefits from the capabilities of PCIe 5.0 ...
EDN

PCI Express System Interconnect Software Architecture

A multi-peer system using a standard-based PCI Express multi-port as the System Interconnect was described in an IDT white paper by Kwok Kong. That white paper described the different address domains ...
EDN

PCI Express Interconnect Software Architecture

A multi-peer system using a standard-based PCI Express multi-port switch as the System Interconnect was described in an IDT white paper by Kwok Kong. That white paper described the different address ...