EDN

Clock generator eliminates input frequency selection pins

Santa Clara, Calif.—Silego Technology Inc. is offering the SLG4421 low power, low jitter EMI reduction spread spectrum clock generator (SSCG) featuring FrequencyAware, a proprietary technology that ...
EDN

Designs with multiple clock domains: New tools avoid clock skew and reduce pattern counts

Nothing accelerates a testability engineer's receding hairline as the addition of further clock domains to the latest SoC or IC design. Avoiding clock skew during test is becoming one of the biggest ...
Electronic Design

Design A Clock-Distribution Strategy With Confidence

Clock-distribution devices create multiple copies of a master clock and distribute them to a variety of integrated circuits. They accept single-ended or differential clock inputs and supply multiple ...