Electronic Design

Clock Domain Crossing and Synchronizers (Part 2): Best Practices

As chip designs grow in complexity and face tighter power constraints, depending on a single clock domain is no longer ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Signal integrity is one of the many challenges faced by chip designers. Deep submicron technologies are unfriendly hosts for the nice, clean signals desired. The culprits that compromise signal ...
Electronic Design

Clock Domain Crossing and Synchronizers (Part 1): Metastability Modeling

Metastability is bound to occur in VLSI designs during clock domain crossing. For a robust and reliable design, metastability needs to be mitigated. To understand how to resolve it and how to build a ...
Dezeen

Maarten Baas creates clock made of people for Schiphol Airport

Dutch designer Maarten Baas enlisted 1,000 volunteers to form the hands of The People's Clock, which provides a choreographed ...