EDN

An overview of SystemVerilog 3.1

SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along ...
Hackaday

FPGA Testbenches Made Easier

You finally finish writing the Verilog for that amazing new DSP function that will revolutionize human society and make you rich. Does it work? Your first instinct, of course, is to blow it into your ...
Hackaday

Learning Verilog For FPGAs: The Tools And Building An Adder

Over the last year we’ve had several posts about the Lattice Semiconductor iCEstick which is shown below. The board looks like an overgrown USB stick with no case, but it is really an FPGA development ...
EDN

How to implement DSP algorithms using the Xilinx Spartan-3E starter board

Editor's Note: This “How To” tutorial is an excerpt from a recently published book: Embedded Design Using Programmable Gate Arrays by Dennis Silage (ISBN-13: 978-1589094864). Dennis is a Professor in ...
Design-Reuse

AMIQ EDA Releases the DVT Debugger Add-On Module for the e language, SystemVerilog, Verilog, and VHDL

AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development, today ...
Design-Reuse

Easier UVM Sequences - SystemVerilog UVM Sequence and Task Equivalence

SystemVerilog [1] UVM [2] sequences [4][5] are a powerful way to model stimulus and response for functional verification. Unfortunately using SystemVerilog UVM sequences can require an extensive ...