EDN

Gabe’s Commentary: Verilog, SystemVerilog, or both

Four years ago, as the semiconductor industry process technology crossed below 193 nanometers, the number of transistors available to a design team made it necessary to explore new design methods at a ...
EDN

DESIGN LANGUAGES: Verisity verification tools tuned for SystemVerilog

Santa Cruz, Calif. — Verisity's Specman environment and the SystemVerilog language once seemed like bitter rivals. Cadence Design Systems Inc. this week will preside over a marriage of the two with ...
Electronics Weekly

The year of SystemVerilog tools

As the great physicist Niels Bohr once jokingly remarked, predictions are very difficult, especially with respect to the future. Although I am in no position to argue with a scientist of Bohr’s ...
Business Wire

Verific Ships First Commercially Available SystemVerilog Parser

Verific Design Automation, the leading provider of Verilog and VHDL front ends for electronic design automation (EDA) applications, today announced that it is shipping the first commercially available ...
Yahoo Finance

Verific's SystemVerilog, VHDL Parsers Chosen by Flexras Technologies to Serve as Front End for FPGA-Based Prototyping Tool

ALAMEDA, CA--(Marketwired - Aug 5, 2014) - Verific Design Automation today announced Flexras Technologies, provider of high-performance partitioning software, has implemented its industry-standard, ...
Electronic Design

Tool Automates Generation Of SystemVerilog Testbenches

THE SYSTEMVERILOG INFRASTRUCTURE is built out further with Synopsys' introduction of Pioneer-NTB. This testbenchautomation tool delivers native SystemVerilog testbench generation to users of ...
Design-Reuse

AMIQ EDA Releases the DVT Debugger Add-On Module for the e language, SystemVerilog, Verilog, and VHDL

AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development, today ...
Design-Reuse

TransEDA adds SystemVerilog support and Advanced Rule checking to its leading Verification Navigator tool suite

Eastleigh UK - Paris France, January 24, 2005 – TransEDA, the leader in coverage and ready-to-use verification solutions for electronic designs, today announces SystemVerilog support in new versions ...
Semiconductor Engineering

Things You Never Knew About System Verilog

System Verilog is considered the current standard for a combined hardware description and verification language, and has been welcomed with open arms since it was approved by IEEE in 2005. Its ...