TSMC claims that it's going to close the gap with Intel at 10-nanometers, while analysts at Bernstein Research claim otherwise. Let's take a closer look at what exactly Bernstein's analysts are ...

PMOS transistors are less vulnerable to substrate noise since they’re placed in separate wells; designers implement guard rings to attenuate the substrate noise propagation. However, substrate noise ...

Even as industry moves into the era of the high k metal gate (HKMG) and FinFET transistor, chipmakers continue to seek ways to improve device performance. One of the latest advances and the subject of ...

The Nature Index 2025 Research Leaders — previously known as Annual Tables — reveal the leading institutions and countries/territories in the natural and health sciences, according to their output in ...

In our previous post Low Power LDO Design Techniques for Really Small Profile Applications, Part 1, we reviewed LDO design tradeoffs using an NMOS pass transistor. This design approach is proven good ...

Device scaling is getting much harder at each new process node. Even defining what it means is becoming a challenge. In the past, gate length and metal pitch went down and device density went up.

All operational amplifier (op-amp) datasheets have an input voltage range limitation called the common-mode range. Strictly speaking, the common-mode voltage is the average voltage on the two inputs ...

LTSpice is a tool that every electronics nerd should have at least a basic knowledge of. Those of us who work professionally in the analog and power worlds rely heavily on the validity of our ...

In a note from Bernstein Research (via Barron's), analysts Mark Li and David Dai question the belief that Taiwan Semiconductor will close the chip manufacturing technology gap with Intel . The ...